The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a memory cell and methods associated with forming and using such structures.
Static random access memory (SRAM) or dynamic random access memory (DRAM) may be used, for example, to temporarily store data in a computer system. An SRAM or DRAM device includes an array of memory cells in which each memory cell retains a single bit of data during operation. Each SRAM memory cell may have a 6-transistor (6T) design that includes a pair of cross-coupled inverters and a pair of access transistors connecting the inverters to complementary bit lines. The two access transistors are controlled by word lines, which are used to select the SRAM memory cell for read or write operations. When continuously powered, the memory state of an SRAM persists without the need for data refresh operations.
Conventional DRAM memory cells may have a one transistor-one capacitor (1T-1C) design that includes a dedicated storage capacitor to store data in the form of electric charge, and a single metal-oxide semiconductor field-effect transistor (MOSFET) to access the storage capacitor for read and write operations.
Resistive random access memory (ReRAM) and magnetic random access memory (MRAM) provide embedded non-volatile memory technologies that contrast with other types of single-transistor memory technologies, such as DRAM. Because ReRAM and MRAM memory elements are non-volatile, stored data is retained when the memory elements are not powered, which contrasts with SRAM in which the stored data is eventually lost when unpowered and DRAM in which the stored data is lost if not periodically refreshed.
Improved structures for a memory cell and methods associated with forming and using such structures are needed.